PROPOSED THERMAL MODEL OF SILICON-ON-INSULATOR (SOI) INTEGRATED CIRCUITS

The Silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structure with a layer of buried silicon oxide added to isolate the device body and the silicon substrate can significantly cut down source and drain depletion capacitances and can reduce the effect of short channel. Though, the low thermal conductivity of the buried oxide (BOX) can cause local heating, changed electrical properties, altered heat flow down interconnects, and failure of thermal devices. The current thermal models that are presently used in simulation of a circuit to account for thermal effects do not accurately capture the heat flow in the devices. However, accurate models rely on large network circuits or arithmetic simulations which does not execute speedily enough for large scale integrated circuit (LSIC) simulation. The drive of this research work is to advance a method that is efficient balance between accuracy, adaptability and speed and can be used in large scale simulation. The approach will integrate efficient SOI device thermal model and communicate thermal model into integrated circuit (IC) simulation, and will offer accurate, effective and efficient electro-thermal simulation tool for large scale SOI integrated circuit structure.